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pre - production this is a product in the pre - production phase of development . device ramtron international corporation characterization is complete and ramtron does not expect to change 1850 ramtron drive, colorado springs, co 80921 the specifications. ramtron will issue a product change notice if any (800) 545 - fram, (719) 481 - 7000 specification changes are made . www.ramtron.com rev. 2.1 sept. 2011 page 1 of 26 fm31 256/fm31 64 fm3116 / fm3104 integrated processor companion with memory features high integration device replaces multiple parts ? serial nonvolatile memory ? real - time clock (rtc) ? low voltage reset ? watchdog timer ? early power - fail warning/nmi ? two 16 - bit event counters ? serial number with write - lock for security ferroelectric nonvolatile ram ? 4kb , 16kb , 64kb, and 256kb versions ? virtually unlimited read/write endurance ? 38 year data retention (+75 ? c) ? nodelay? writes real - time clock/calendar ? backup current 1 . 4 ? a ? seconds through centuries in bcd format ? tracks leap years through 2099 ? uses standard 32.768 khz crystal (6pf) ? software calibration ? supports battery or capacitor backup processor companion ? active - low reset output for v dd and watchdog ? programmable v dd reset trip point ? manual reset filtered and de bounced ? programmable watchdog timer ? dual battery - backed event counter tracks system intrusions or other events ? comparator for early power - fail interrupt ? 64 - bit progra mmable serial number with lock fast two - wire serial interface ? up to 1 mhz maximum bus frequency ? supports legacy timing for 100 khz & 400 khz ? device select pins for up to 4 memory devices ? rtc, supervisor controlled via 2 - wire interface easy to use configu rations ? operates from 2.7 to 5.5v ? small footprint 14 - pin green soic ( - g) ? low operating current ? - 40 ? c to +85 ? c operation description the fm31 xx is a family of integrated devices that includes the most commonly needed functions for processor - based systems. major features include nonvolatile memory available in various sizes, real - time clock, low - vdd reset, watchdog timer, nonvolatile event counter , lockable 64 - bit serial number area, and general purpose comparator that can be used for an early power - fail (nmi) interrupt or other purpose. the family operates from 2.7 to 5.5v. each fm31 xx provides nonvolatile ram available in sizes including 4kb , 16 kb , 64kb, and 256kb versions. fast write speed and unlimited endurance allow the memory to serve as extra ram or conventional nonvolatile storage. this memory is truly nonvolatile rather than battery backed. the real - time clock (rtc) provides time and dat e information in bcd format. it can be permanently powered from external backup voltage source, either a battery or a capacitor. the timekeeper uses a common external 32.768 khz crystal and provides a calibration mode that allows software adjustment of tim ekeeping accuracy. the processor companion includes commonly needed cpu support functions. supervisory functions include a reset output signal controlled by either a low vdd condition or a watchdog timeout. /rst goes active when vdd drops below a program mable threshold and remains active for 100 ms after vdd rises above the trip point. a programmable watchdog timer runs from 100 ms to 3 seconds. the watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by t he host before the timeout. a flag - bit indicates the source of the reset.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 2 of 26 a general - purpose comparator compares an external input pin to the onboard 1.2v reference. this is useful for generating a power - fail interrupt (nmi) but can be used for any purpos e. the family also includes a programmable 64 - bit serial number that can be locked making it unalterable. additionally it offers a dual battery - backed event counter that tracks the number of rising or falling edges detected on dedicated input pins. pin configuration pin name function cnt1, cnt2 event counter inputs a0, a1 device select inputs cal/pfo cloc k calibration and early power - f ail output /rst reset input/output pfi early power - fail input x1, x2 crystal connections sda serial data scl serial clock vbak battery - backup supply vdd supply voltage vss ground ordering information base configuration memory size operating voltage reset threshold ordering part number fm31256 256kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31256 - g 256kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm31256 - gtr (tape&reel) fm3164 64kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3164 - g 64kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3164 - gtr (tape&reel) fm3116 * 16kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3116 - g 16kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3116 - gtr (tape&reel) fm3104 * 4kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3104 - g 4kb 2.7 - 5.5v 2.6v, 2.9, 3.9, 4.4v fm3104 - gtr (tape&reel) * the fm3116 and fm 3104 devices are eol as of s ept. 2011. vdd vbak scl sda vss x1 x2 cal/pfo cnt1 pfi rst a0 a1 cnt2 1 2 3 4 5 6 7 14 13 12 11 10 9 8
fm3104/16/64/256 rev. 2.1 sept. 2011 page 3 of 26 figure 1. block diagram pin descriptions pin name type pin description a0, a1 input device select inputs are used to address multiple memories on a serial bus. to select the device the address value on the two pins must match the corresponding bits contained in the device address. the device select pins are pulled down internally. cnt1, cnt2 input event counter inputs: these battery - backed inputs increment counters when an edge is detected on the corresponding cnt pin. the polarity is programmable. these pins should not be left floating. t ie to ground if pins are not used. cal/pfo output in calibration mode, this pin supplies a 512 hz square - wave output for clock calibration. in normal operation, this is the early power - fail output. x1, x2 i/o 32.768 khz crystal connection. when using an external oscillator, apply the clock to x1 and a dc m id - level to x2 (see crystal oscillator section for suggestions). /rst i/o active low reset output with weak pull - up. also input for manual reset. sda i/o serial data & address: this is a bi - directional line for the two - wire interface. it is open - drain and is intended to be wire - ord with other devices on the two - wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. a pull - up resistor is required. scl input serial clock: the serial clock line for t he two - wire interface. data is clocked out of the part on the falling edge, and in on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. pfi input early power - fail input: typically connected to an unregulated powe r supply to detect an early power failure. this pin should not be left floating. vbak supply backup supply voltage: a 3v battery or a large value capacitor. if v dd <3.6v and no backup supply is used, this pin should be tied to v dd . if v dd >3.6v and no backup supply is used, this pin should be left floating and the vbc bit should be set. vdd supply supply voltage vss supply ground fram array 2 - wire interface scl sda rst a1, a0 cal/pfo pfi vdd vbak rtc 2.5v - + rtc registers event counters cnt1 cnt2 special function registers s/n x1 x2 lockout lockout + - 1.2v watchdog lv detect switched power 512hz rtc cal. battery backed nonvolatile
fm3104/16/64/256 rev. 2.1 sept. 2011 page 4 of 26 overview the fm31 xx family combines a serial nonvolatile ram with a real - time clock (rtc) and a processor companion. the companion is a highly integrated peripheral including a processor supervisor, a comparator used for early power - fail warning, nonvolatile event counters, and a 64 - bit serial number. the fm31 xx integrates these complementary but distinct functions that share a common interface in a single package. although monolithic, the product is organized as two logical devices, the fram memory and the rtc/companion. fro m the system perspective they appear to be two separate devices with unique ids on the serial bus. the memory is organized as a stand - alone 2 - wire nonvolatile memory with a standard device id value. the real - time clock and supervisor functions are access ed with a separate 2 - wire device id. this allows clock/calendar data to be read while maintaining the most recently used memory address. the clock and supervisor functions are controlled by 25 special function registers. the rtc and event counter circuits are maintained by the power source on the vbak pin, allowing them to operate from battery or backup capacitor power when v dd drops below an internally set threshold. each functional block is described below. memory operation the fm31 xx is a family of products available in different memory sizes including 4kb , 16kb , 64kb, and 256kb. the family is software compatible, all versions use consistent two - byte addressing for the memory device. this makes the lowest density device different from its stand - alone memory counterparts but makes them compatible within the entire family. memory is organized in bytes, for example the 6 4kb memory is 8 1 92 x 8 and the 256kb memory is 32 768 x 8. the memory is based on fram technology. therefore it can be treated as ram and is read or written at the speed of the two - wire bus with no delays for write operations. it also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. the 2 - wire interface protocol is described fur ther on page 1 5 . the memory array can be write - protected by software. two bits in the processor companion area (wp0, wp1 in register 0bh) control the protection setting as shown in the following table. based on the setting, the protected addresses cannot be written and the 2 - wire interface will not acknowledge any data to protected addresses. the special function registers containing these bits are described in detail below. write protect addresses wp1 wp0 none 0 0 bottom 1/4 0 1 bottom 1/2 1 0 full arra y 1 1 processor companion in addition to nonvolatile ram, the fm31 xx family incorporates a highly integrated processor companion. it includes a low voltage reset, a programmable watchdog timer, battery - backed event counters, a comparator for early power - fa il detection or other purposes, and a 64 - bit serial number. processor supervisor supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. all fm31 xx de vices have a reset pin (/rst) to drive the processor reset input during power faults (and power - up) and software lockups. it is an open drain output with a weak internal pull - up to v dd . this allows other reset sources to be wire - ord to the /rst pin. when v dd is above the programmed trip point, /rst output is pulled weakly to v dd . if v dd drops below the reset trip point voltage level (v tp ) the /rst pin will be driven low. it will remain low until v dd falls too low for circuit operation which is the v rst lev el. when v dd rises again above v tp , /rst will continue to drive low for at least 100 ms (t rpu ) to ensure a robust system reset at a reliable v dd level. after t rpu has been met, the /rst pin will return to the weak high state. while /rst is asserted, serial bus activity is locked out even if a transaction occurred as v dd dropped below v tp . a memory operation started while v dd is above v tp will be completed internally. figure 2 below illustrates the reset operation in response to the v dd voltage. figure 2. low voltage reset the bits vtp1 and vtp0 control the trip point of the low voltage detect circuit. they are located in register 0bh, bits 1 and 0. vdd vtp t rpu rst
fm3104/16/64/256 rev. 2.1 sept. 2011 page 5 of 26 v tp vtp1 vtp0 2.6v 0 0 2.9v 0 1 3.9v 1 0 4.4v 1 1 the watchdog timer can also be used to assert the reset signal (/rst). the watchdog is a free running programmable timer. the period can be software programmed from 100 ms to 3 seconds in 100 ms increments via a 5 - bit nonvolatile register. all programmed s ettings are minimum values and vary with temperature according to the operating specifications. the watchdog has two additional controls associated with its operation, a watchdog enable bit (wde) and timer restart bits (wr). both the enable bit must be set and the watchdog must timeout in order to drive /rst active. if a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. if wde=0 , the watchdog timer runs but a watchdog fault will not cause /rst to be asserted low . the wtr flag will be set , indicating a watchdog fault . this setting is useful during software develop ment and the developer do es n o t want /rst to drive. note that setting the maximum timeout setting (11111b) disables the counter to save power. the second control is a nibble that restarts the timer preventing a reset. the timer should be restarted after changing the timeout value. the watchdog timeout val ue is located in register 0ah, bits 4 - 0, and the watchdog enable is bit 7. the watchdog is restarted by writing the pattern 1010b to the lower nibble of register 09h. writing this pattern will also cause the timer to load new timeout values. writing other patterns to this address will not affect its operation. note the watchdog timer is free - running. prior to enabling it, users should restart the timer as described above. this assures that the full timeout period will be set immediately after enabling. the watchdog is disabled when v dd is below v tp . the following table summarizes the watchdog bits. a block diagram follows. watchdog timeout wdt4 - 0 0ah, bits 4 - 0 watchdog enable wde 0ah, bit 7 watchdog restart wr3 - 0 09h, bits 3 - 0 figure 3. watchdog timer manual reset the /rst pin is bi - directional and allows the fm31 xx to filter and de - bounce a manual reset switch. the /rst input detects an external low condition and responds by driving the /rs t signal low for 100 ms. figure 4. manual reset note that an internal weak pull - up on /rst eliminates the need for additional external components. reset flags in case of a reset condition, a flag will be set to indicate the source of the reset. a low v dd reset is indicated by the por flag, register 09h bit 6. a watchdog reset is indicated by the wtr flag, register 09h bit 7. note that the flags are internally set in response to reset sources, but they must be cleared by the user. when the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. early power fail comparator an early power fail warning can be provided to the processor well before v dd drops out of spec. the comparator is used to create a power fail interrupt (nmi). this can be accomplished by connecting the pfi pin to the unregulated power supply via a resistor divider. an application circuit is shown below. figure 5. comparator as early power - fail warning + - 1.2v ref regulator vdd fm31xx to mcu nmi input cal/pfo pfi fm31xx reset switch rst mcu switch behavior rst fm31xx drives 100 ms (min.) timebase counter watchdog timeout 100 ms clock wde /rst wr3 - 0 = 1010b to restart
fm3104/16/64/256 rev. 2.1 sept. 2011 page 6 of 26 the voltage on the pfi input pin is compared to an onboard 1.2v reference. when the pfi input voltage drops below this threshold, the comparator will drive the cal/pfo pin to a low state. the comparator has 10 0 mv (max ) of hysteres is to reduce noise sensit ivity , only for a rising pfi signal . for a falling pfi edge, there is no hysteresis. the comparator is a general purpose device and its application is not limited to the nmi function. the comparator is not integrated into the special function registers except as it shares its output pin with the cal output. when the rtc calibration mode is invoked by setting the cal bit (register 00h, bit 2), the cal/pfo output pin will be driven with a 512 hz square wave and the comparator will be ignored. since most users only invoke the calibration mode during production, this should have no impact on system operations using the comparator. note: the maximum voltage on the comparator input pfi is limited to 3.75v under normal operating conditions. event counter the fm31 xx offers the user two battery - backed event counters. input pins cnt1 and cnt2 are programmable edge detectors. each clocks a 16 - bit counter. when an edge occurs, the counters will increment their respective registers. counter 1 is located in registers 0dh and 0eh, counter 2 is located in registers 0fh and 10h. these register values can be read anytime vdd is above vtp, and th ey will be incremented as long as a valid vbak power source is provided. to read, set the rc bit register 0ch bit 3 to 1. this takes a snapshot of all four counter bytes allowing a stable value even if a count occurs during the read. the registers can be w ritten by software allowing the counters to be cleared or initialized by the system. counts are blocked during a write operation. the two counters can be cascaded to create a single 32 - bit counter by setting the cc control bit (register 0ch). when cascaded , the cnt1 input will cause the counter to increment. cnt2 is not used in this mode. figure 6. event counter the control bits for event counting are located in register 0ch. counter 1 polarity is bit c1p, bit 0; counter 2 polarity is c2p, bit 1; the cascade control is cc, bit 2; and the read counter bit is rc bit 3. the polarity bits must be set prior to setting the counter value(s). if a polarity bit is changed, the counter may inadvertently increment. if the counter pins are not being used, tie them to gr ound. serial number a memory location to write a 64 - bit serial number is provided. it is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. the 8 bytes of data and the lock bit are all accessed via the device id for the processo r companion. therefore the serial number area is separate and distinct from the memory array. the serial number registers can be written an unlimited number of times, so these locations are general purpose memory. however once the lock bit is set the value s cannot be altered and the lock cannot be removed. once locked the serial number registers can still be read by the system. the serial number is located in registers 11h to 18h. the lock bit is snl, register 0bh bit 7. setting the snl bit to a 1 disables writes to the serial number registers, and the snl bit cannot be cleared . real - time clock operation the real - time clock (rtc) is a timekeeping device that can be battery or capacitor backed for permanently - powered operation. it offers a software calibrati on feature that allows high accuracy. the rtc consists of an oscillator, clock divider, and a register system for user access. it divides down the 32.768 khz time - base and provides a minimum resolution of seconds (1hz). static registers provide the user with read/write access to the time values. it includes registers for seconds, minutes, hours, day - of - the - week, date, months, and years. a block diagram (figure 7) illustrates the rtc function. the user registers are synchronized with the timekeeper core using r and w bits in register 00h described below. changing the r bit from 0 to 1 transfers timekeeping information from the core into holding registers that can be read by the user. if a timekeeper update is pending when r is set, then the core will be u pdated prior to loading the user registers. the registers are frozen and will not be updated again until the r bit is cleared to 0. r is used for reading the time. setting the w bit to 1 locks the user registers. clearing it to 0 causes the values in the user registers 16 - bit counter cnt1 cc cnt2 c1p c2p 16 - bit counter
fm3104/16/64/256 rev. 2.1 sept. 2011 page 7 of 26 to be loaded into the timekeeper core. w is used for writing new time values. users should be certain not to load invalid values, such as ffh, to the timekeeping registers. updates to the timekeeping core occur continuously except when locke d. backup power the real - time clock/calendar is intended to be permanently powered. when the primary system power fails, the voltage on the v dd pin will drop. when v dd is less 2.5v , the rtc (and event counters) will switch to the backup power supply on v bak . the clock operates at extremely low current in order to maxim ize battery or capacitor life. however, an advantage of combining a clock function with fram memory is that data is not lost regardless of the backup power source. the i bak current varies w ith temperature and voltage (see dc parametric table). the following graph shows i bak as a function of v bak . th ese curves are useful for calculating backup time when a capacitor is used as the v bak source. figure 7 . i bak vs. v bak voltage the minimum v bak voltage varies linearly with temperature. t he user can expect the minimum v bak voltage to be 1.23v at +85c and 1. 9 0 v at - 40c . th e tested limit is 1.55v at +25 c . the minimum v bak voltage has been characterized at - 40c and +85c but is not 100% tested. figure 8 . v bak ( min.) vs. temperature trickle charger to facilitate capacitor backup the v bak pin can optionally provide a trickle charge current. when the vbc bit, register 0bh bi t 2, is set to 1 the v bak pin will source approximately 1 5 a until v bak reaches v dd or 3.75v whichever is less. in 3v systems, this charges the capacitor to v dd without an external diode and resistor charger. in 5v systems, it provides the same convenienc e and also prevents the user from exceeding the v bak maximum voltage specification. in the case where no battery is used, the v bak pin should be tied according to the following conditions: ? for 3.3v systems, v bak should be tied to v dd . this assumes v dd does not exceed 3.75v. ? for 5v systems, attach a 1 f capacitor to v bak and turn the trickle charger on. the v bak pin will charge to the internal backup voltage which regulates itself to about 3.6v. v bak should not be tied to 5v since the v bak (max) spec ification will be exceeded. a 1 f capacitor will keep the companion functions working for about 1.5 second. although v bak may be connected to v ss , this is not recommended if the companion is used. none of the companion functions will operate below abo ut 2.5v. ? note: systems using lithium batteries should clear the vbc bit to 0 to prevent battery charging. the v bak circuitry includes an internal 1 k ? series resistor as a safety element.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 8 of 26 figure 9 . real - time clock core block diagram calibration when the cal bit in a register 00h is set to 1, the clock enters calibration mode. in calibration mode, the cal/pfo output pin is dedicated to the calibration function and the power fail ou tput is temporarily unavailable. calibration operates by applying a digital correction to the counter based on the frequency error. in this mode, the cal/pfo pin is driven with a 512 hz (nominal) square wave. any measured deviation from 512 hz translates i nto a timekeeping error. the user converts the measured error in ppm and writes the appropriate correction value to the calibration register. the correction factors are listed in the table below. positive ppm errors require a negative adjustment that remov es pulses. negative ppm errors require a positive correction that adds pulses. positive ppm adjustments have the cals (sign) bit set to 1, where as negative ppm adjustments have cals = 0. after calibration, the clock will have a maximum error of ? 2.17 ppm or ? 0.09 minutes per month at the calibrated temperature. the calibration setting is stored in fram so is not lost should the backup source fail. it is accessed with bits cal.4 - 0 in register 01h. this value only can be written when the cal bit is set to a 1. to exit the calibration mode, the user must clear the cal bit to a 0. when the cal bit is 0, the cal/pfo pin will revert to the power fail output function. crystal oscillator the crystal oscillator is designed to use a 6 pf crystal without the need fo r external components, such as loading capacitors. the fm31 xx device has built - in loading capacitors that match the crystal. if a 32.768khz crystal is not used, an external oscillator may be connected to the fm31 xx . apply the oscillator to the x1 pin. i ts high and low voltage levels can be driven rail - to - rail or amplitudes as low as approximately 500mv p - p. to ensure proper operation, a dc bias must be applied to the x2 pin. it should be centered between the high and low levels on the x1 pin. this can be accomplished with a voltage divider. figure 10 . external oscillator in the example, r1 and r2 are chosen such that the x2 voltage is centered around the x1 oscillator drive levels. if you wish to avoid the dc current, you may choose to drive x1 with an external clock and x2 with an inverted clock using a cmos inverter. layout requirement s the x1 and x2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noi se or extra loading . to reduce rtc clock er rors from signal switching noise, a guard ring must be pla ced around these pads and the guard ring grounded . sda and scl traces should be routed away from the x1/x2 pads. the x1 and x2 trace lengths should be less than 5 mm. the use of a groun d plane on the backside or inner board layer is preferred. see layout example. red is the top layer, g reen is the bottom layer. x1 x2 vdd fm31 xx r1 r2 32.768 khz crystal oscillator clock divider update logic 512 hz w r seconds 7 bits minutes 7 bits hours 6 bits date 6 bits months 5 bits years 8 bits cf days 3 bits user interface registers 1 hz /oscen
fm3104/16/64/256 rev. 2.1 sept. 2011 page 9 of 26 layout for surface mount crystal layout for through hole crystal (red = top layer, green = bottom layer) (red = top layer, green = bottom layer) vdd scl sda x2 x1 pfi vbak vdd scl sda x2 x1 pfi vbak
fm3104/16/64/256 rev. 2.1 sept. 2011 page 10 of 26 calibration adjustments positive calibration for slow clocks: calibration will achieve ? 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 negative calibration for fast clocks: calibration will achieve ? 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111
fm3104/16/64/256 rev. 2.1 sept. 2011 page 11 of 26 register map the rtc and processor companion functions are accessed via 25 special function registers mapped to a separate 2 - wire device id. the interface protocol is described below. the registers contain timekeeping data, control bits, or information flags. a description of each register follows the summary table below. register map summary table nonvolatile = battery - backed = note: when the device is first powered up and programmed , all registers must be written because the battery - backed register values cannot be guaranteed. the table below shows the default values of the non - volatile regi sters . all other register values should be treated as unknown. default register values address hex value 18h 0x00 17h 0x00 16h 0x00 15h 0x00 14h 0x00 13h 0x00 12h 0x00 11h 0x00 0bh 0x00 0ah 0x1f 01h 0x80 data address d7 d6 d5 d4 d3 d2 d1 d0 function range serial number byte 7 serial number 7 ffh serial number byte 6 serial number 6 ffh serial number byte 5 serial number 5 ffh serial number byte 4 serial number 4 ffh serial number byte 3 serial number 3 ffh serial number byte 2 serial number 2 ffh serial number byte 1 serial number 1 ffh serial number byte 0 serial number 0 ffh 10h counter 2 msb event counter 2 msb ffh 0fh counter 2 lsb event counter 2 lsb ffh 0eh counter 1 msb event counter 1 msb ffh 0dh counter 1 lsb event counter 1 lsb ffh 0ch rc cc c2p c1p event count control 0bh snl - - wp1 wp0 vbc vtp1 vtp0 companion control 0ah wde - - wdt4 wdt3 wdt2 wdt1 wdt0 watchdog control 09h wtr por lb - wr3 wr2 wr1 wr0 watchdog restart/flags 08h 10 years years years 00-99 07h 0 0 0 10 mo months month 1-12 06h 0 0 10 date date date 1-31 05h 0 0 0 0 0 day day 1-7 04h 0 0 10 hours hours hours 0-23 03h 0 10 minutes minutes minutes 0-59 02h 0 10 seconds seconds seconds 0-59 01h /oscen reserved cals cal4 cal3 cal2 cal1 cal0 cal/control 00h reserved cf reserved reserved reserved cal w r rtc control 18h 17h 11h 16h 15h 14h 13h 12h
fm3104/16/64/256 rev. 2.1 sept. 2011 page 12 of 26 register description address description 18h serial number byte 7 d7 d6 d5 d4 d3 d2 d1 d0 sn.63 sn.62 sn.61 sn.60 sn.59 sn.58 sn.57 sn.56 upper byte of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 17h serial number byte 6 d7 d6 d5 d4 d3 d2 d1 d0 sn.55 sn.54 sn.53 sn.52 sn.51 sn.50 sn.49 sn.48 byte 6 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 16h serial number byte 5 d7 d6 d5 d4 d3 d2 d1 d0 sn.47 sn.46 sn.45 sn.44 sn.43 sn.42 sn.41 sn.40 byte 5 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 15h serial number byte 4 d7 d6 d5 d4 d3 d2 d1 d0 sn.39 sn.38 sn.37 sn.36 sn.35 sn.34 sn.33 sn.32 byte 4 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 14h serial number byte 3 d7 d6 d5 d4 d3 d2 d1 d0 sn.31 sn.30 sn.29 sn.28 sn.27 sn.26 sn.25 sn.24 byte 3 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 13h serial number byte 2 d7 d6 d5 d4 d3 d2 d1 d0 sn.23 sn.22 sn.21 sn.20 sn.19 sn.18 sn.17 sn.16 byte 2 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 12h serial number byte 1 d7 d6 d5 d4 d3 d2 d1 d0 sn.15 sn.14 sn.13 sn.12 sn.11 sn.10 sn.9 sn.8 byte 1 of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 11h serial number byte 0 d7 d6 d5 d4 d3 d2 d1 d0 sn.7 sn.6 sn.5 sn.4 sn.3 sn.2 sn.1 sn.0 lsb of the serial number. read/write when snl=0, read - only when snl=1. nonvolatile. 10h counter 2 msb d7 d6 d5 d4 d3 d2 d1 d0 c2.15 c2.14 c2.13 c2.12 c2.11 c2.10 c2.9 c2.8 event counter 2 msb. increments on overflows from counter 2 lsb. battery - backed, read/write. 0fh counter 2 lsb d7 d6 d5 d4 d3 d2 d1 d0 c2.7 c2.6 c2.5 c2.4 c2.3 c2.2 c2.1 c2.0 event counter 2 lsb. increments on programmed edge event on cnt2 input or overflows from counter 1 msb when cc=1. battery - backed, read/write . 0eh counter 1 msb d7 d6 d5 d4 d3 d2 d1 d0 c1.15 c1.14 c1.13 c1.12 c1.11 c1.10 c1.9 c1.8 event counter 1 msb. increments on overflows from counter 1 lsb. battery - backed, read/write. 0dh counter 1 lsb d7 d6 d5 d4 d3 d2 d1 d0 c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 event counter 1 lsb. increments on programmed edge event on cnt1 input. battery - backed, read/write.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 13 of 26 0ch event counter control d7 d6 d5 d4 d3 d2 d1 d0 - - - - rc cc c2p c1p rc read counter. setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. the rc bit will be automatically cleared. cc counter cascade. when cc=0, the event counters operate independently according to t he edge programmed by c1p and c2p respectively. when cc=1, the counters are cascaded to create one 32 - bit counter. the registers of counter 2 represent the most significant 16 - bits of the counter and cnt1 is the controlling input. bit c2p is dont care w hen cc=1. battery - backed, read/write. c2p cnt2 detects falling edges when c2p = 0, rising edges when c2p = 1. c2p is dont care when cc=1. the value of event counter 2 may inadvertently increment if c2p is changed. battery - backed, read/write. c1p cnt1 detects falling edges when c1p = 0, rising edges when c1p = 1. the value of event counter 1 may inadvertently increment if c1p is changed. battery - backed, read/write. 0bh companion control d7 d6 d5 d4 d3 d2 d1 d0 snl - - wp1 wp0 vbc vtp1 vtp0 snl serial number lock. setting to a 1 makes registers 11h to 18h and snl permanently read - only. snl cannot be cleared once set to 1. nonvolatile, read/write. wp1 - 0 write protect. these bits control the write protection of the memory array. nonvolatile, rea d/write. write protect addresses wp1 wp0 none 0 0 bottom 1/4 0 1 bottom 1/2 1 0 full array 1 1 vbc vbak charger control. setting vbc to 1 causes a 15 a trickle charge current to be supplied on vbak. clearing vbc to 0 disables the charge current. nonvolatile, read/write. vtp1 - 0 vtp select. these bits control the reset trip point for the low vdd reset function. nonvolatile, read/write. vtp vtp1 vtp0 2.6v 0 0 2.9v 0 1 3.9v 1 0 4.4v 1 1 0ah watchdog control d7 d6 d5 d4 d3 d2 d1 d0 wde - - wdt4 wdt3 wdt2 wdt1 wdt0 wde watchdog enable. when wde=1 , a watchdog timer fault will cause the /rst signal to go active. when wde = 0 the timer runs but has no effect on /rst , however the wtr flag will be set when a fault occurs . note as the timer is free - running, users should restart the timer using wr3 - 0 prior to setting wde=1. this ass ures a full watchdog timeout interval occurs. nonvolatile, read/write. wdt4 - 0 watchdog timeout. indicates the minimum watchdog timeout interval with 100 ms resolution. new watchdog timeouts are loaded when the timer is restarted by writing the 1010b patte rn to wr3 - 0. nonvolatile, read/write. watchdog timeout wdt4 wdt3 wdt2 wdt1 wdt0 invalid C default 100 ms 0 0 0 0 0 100 ms 0 0 0 0 1 200 ms 0 0 0 1 0 300 ms 0 0 0 1 1 . . . 2000 ms 1 0 1 0 0 2100 ms 1 0 1 0 1 2200 ms 1 0 1 1 0 . . . 2900 ms 1 1 1 0 1 3000 ms 1 1 1 1 0 disable counter 1 1 1 1 1
fm3104/16/64/256 rev. 2.1 sept. 2011 page 14 of 26 09h watchdog restart & flags d7 d6 d5 d4 d3 d2 d1 d0 wtr por lb - wr3 wr2 wr1 wr0 wtr watchdog timer reset flag: when a watchdog timer fault occurs, the wtr bit will be set to 1. it must be cleared by the user. note that both wtr and por could be set if both reset sources have occurred since the flags were cleared by the user. battery - backed. read/writ e (internally set, user can clear bit). por powe r - on reset flag: when the /rst pin is activated by v dd < v tp , the por bit will be set to 1. it must be cleared by the user. note that both wtr and por could be set if both reset sources have occurred since the flags were cleared by the user. battery - backed. read/writ e (internally set, user can clear bit). lb low backup flag: on power up, if the vbak source is below the minimum voltage to operate the rtc and event counters, this bit will be set to 1. the user should clear it to 0 when initializing the system. battery - backed. read/write (internal ly set, user can clear bit). wr3 - 0 watchdog restart: writing a pattern 1010b to wr3 - 0 restarts the watchdog timer. the upper nibble contents do not affect this operation. writing any patte rn other than 1010b to wr3 - 0 has no effect on the timer. this allows u sers to clear the wtr, por , and lb flags without affecting the watchdog timer. battery - backed, write - only. 08h timekeeping C years d7 d6 d5 d4 d3 d2 d1 d0 10 year.3 10 year.2 10 year.1 10 year.0 year.3 year.2 year.1 year.0 contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0 - 99. battery - backed, read/write. 07h timekeeping C months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10 month month.3 month.2 month.1 month.0 contains the bcd digits for the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. the range for the register is 1 - 12. battery - backed, read/write. 06h timekeepin g C date of the month d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range for the register is 1 - 31. battery - backed, read/write. 05h timekeep ing C day of the week d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day.2 day.1 day.0 lower nibble contains a value that correlates to day of the week. day of the week is a ring counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. battery - backed, read/w rite. 04h timekeeping C hours d7 d6 d5 d4 d3 d2 d1 d0 0 0 10 hours.1 10 hours.0 hours.3 hours2 hours.1 hours.0 contains the bcd value of hours in 24 - hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0 - 23. battery - backed, read/write. 0 3h timekeeping C minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0 - 59. battery - backed, read/write. 02h timekeeping C seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10 sec.2 10 sec.1 10 sec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0 - 59. battery - backed, read/write.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 15 of 26 01h cal/control d7 d6 d5 d4 d3 d2 d1 d0 oscen reserved cals cal.4 cal.3 cal.2 cal.1 cal.0 /oscen /oscillator enable. when set to 1, the oscillator is halted. when set to 0, the oscillator runs. disabling the oscillator can save battery power during storage. on a power - up without battery, this bit is set to 1. battery - backed, read/write. reserved reserved bits. do not use. should remain set to 0. cals calibration sign. determines if the calibration adjustment is applied as an addition to or as a subtraction from the time - base. calibration is explained on page 7. nonvolatile, read/write. cal.4 - 0 t hese five bits control the calibration of the clock. nonvolatile, read/write. 00h flags/control d7 d6 d5 d4 d3 d2 d1 d0 reserved cf reserved reserved reserved cal w r cf century overflow flag. this bit is set to a 1 when the values in the years register overflows from 99 to 00. this indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. the user should record the new century information as needed. this b it is cleared to 0 when the flag register is read. it is read - only for the user. battery - backed . cal calibration mode. when set to 1, the clock enters calibration mode. when cal is set to 0, the clock operates normally, and the cal/pfo pin is controlled b y the power fail comparator. battery - backed, r ead/write. w write time. setting the w bit to 1 freezes the clock . the user can then write the timekeeping registers with updated values . res etting the w bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters and restarts the clock . battery - backed, r ead/write. r read time. setting the r bit to 1 copies a static image of the timekeeping core and place it into the user registers. the user can then read them without conc erns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. battery - backed, r ead/write. reserved reserved bits. do not use. should remain set to 0.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 16 of 26 two - wire interface the fm31 xx employs an industry standard two - wire bus that is familiar to many users. this product is unique since it incorporates two logical devices in one chip. each logical device can be accessed individually. although monolithic, it appears to the system software to be two separate products. one is a memory device. it has a slave address (slave id = 1010b) that operates the same as a stand - alone memory device. the second device is a real - time clock and processor companion which have a unique slave address (slave id = 1101b). by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm31 xx is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions: start, stop, data bit, and acknowledge. the figure below illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications secti on. figure 11 . data transfer protocol start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all read and write transactions begin with a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm31 xx for a new operation. if the power supply drops below the specified vtp during operation, any 2 - wire transaction in progress will be aborted and the system must issue a start condition prior to performing another operation. stop conditi on a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations must end with a stop condition. if an operation is pending when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge (ack) takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter must release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condi tion is a no - acknowledge (nack) and the operation is aborted. the receiver might nack for two distinct reasons. first is that a byte transfer fails. in this case, the nack ends the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not send an ack to deliberately terminate an operation. for example, during a read operation, the fm31 xx will continue to place data onto the bus as long as the receiver sends acks (and clocks). when a read operation is complete and no more data is needed, the receiver must nack the last byte. if the receiver acks the last byte, this will cause the fm31 xx to attempt to drive the bus on the next cloc k while the master is sending a new command such as a stop. stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda
fm3104/16/64/256 rev. 2.1 sept. 2011 page 17 of 26 slave address the first byte that the fm31 xx expects after a start condition is the slave address. as shown in figures below, the slave address contains the slave id, device select address, and a bit that specifies if the transaction is a read or a write. the fm31 xx has two slave addresses (slave ids) associated with two logical devices. to access the memory device, bits 7 - 4 should be set to 1010b. the other logical device within the fm31 xx is t he real - time clock and companion. to access this device, bits 7 - 4 of the slave address should be set to 1101b. a bus transaction with this slave address will not affect the memory in any way. the figures below illustrate the two slave addresses. the dev ice select bits allow multiple devices of the same type to reside on the 2 - wire bus. the device select bits (bits 2 - 1) select one of four parts on a two - wire bus. they must match the corresponding value on the external address pins in order to select the d evice. bit 0 is the read/write bit. a 1 indicates a read operation, and a 0 indicates a write operation. figure 1 2 . slave address - memory figure 1 3 . slave address C companion addressing overview C memory after the fm31 xx acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes. this is true for all members of the family. therefore the 4kb and 16kb configurations will be addressed differently f rom stand alone serial memories but the entire family will be upwardly compatible with no software changes. the first is the msb (upper byte). for a given density unused address bits are dont cares, but should be set to 0 to maintain upward compatibility . following the msb is the lsb (lower byte) which contains the remaining eight address bits. the address is latched internally. each access causes the latched address to be incremented automatically. the current address is the value that is held in the lat ch, either a newly written value or the address following the last access. the current address will be held as long as vdd > vtp or until a new value is written. accesses to the clock do not affect the current memory address. reads always use the current a ddress. a random read address can be loaded by beginning a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm31 xx increments the internal address. this allows the next sequential byte to be acc essed with no additional addressing externally. after the last address is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. addressing overview C rtc & companion the rtc and processor companion operate in a similar manner to the memory, except that it uses only one byte of address. addresses 00h to 18h correspond to special function registers. attempting to load addresses above 18h is an illegal conditio n; the fm31 xx will return a nack and abort the 2 - wire transaction. data transfer after the address information has been transmitted, data transfer between the bus master and the fm31 xx begins. for a read, the fm31 xx will place 8 data bits on the bus then wait for an ack from the master. if the ack occurs, the fm31 xx will transfer the next byte. if the ack is not sent, the fm31 xx will end the read operation. for a write operation, the fm31 xx will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory write operation all memory writes begin with a slave address, then a memory address. the bus master indicates a write operation by setting the slave address lsb to a 0. after addressing, t he bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap to 0000h. internally, the actual memory write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the 1 1 0 1 x a1 a0 r/w slave id 7 6 5 4 3 2 1 0 device select 1 0 1 0 x a1 a0 r/w slave id device select 7 6 5 4 3 2 1 0
fm3104/16/64/256 rev. 2.1 sept. 2011 page 18 of 26 user desires to abort a write without altering the memory contents, this should be done using a start or stop condi tion prior to the 8 th data bit. the figures below illustrate a single - and multiple - writes to memory. figure 1 4 . single byte memory write figure 1 5 . multiple byte memory write memory read operation there are two types of memory read operations. they are current address read and selective address read. in a current address read, the fm31 xx uses the internal address latch to supply the address. in a selective read, the user performs a procedure to first set the address to a specific value. current address & sequential read as mentioned above the fm31 xx uses an internal latch to supply the address for a read operation. a current addr ess read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete device address, the fm31 xx will begin shifting data out from the current address on the next clock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm31 xx should read out the next sequential byte. there are four ways to terminate a read operation. failing to properly terminate the read will m ost likely create a bus contention as the fm31 xx attempts to read out additional data onto the bus. the four valid methods follow. 1. the bus master issues a nack in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below and is preferred. 2. the bus master issues a nack in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle. if the internal address reaches the top of memory, it will wrap around to 0000h on the next read cycle. the figures below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a random address location as the starting p oint for a read operation. this involves using the first s a slave address 0 address msb a data byte a p by master by fm31xxx start address & data stop acknowledge address lsb a s a slave address 0 address msb a data byte a p by master by fm31xxx start address & data stop acknowledge address lsb a data byte a
fm3104/16/64/256 rev. 2.1 sept. 2011 page 19 of 26 three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb set to 0. t his specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm31 xx acknowledges the address, the bus master issues a start condition. this simultan eously aborts the write operation and allows the read command to be issued with the slave address lsb set to a 1. the operation is now a read from the current address. read operations are illustrated below. rtc/companion write operation all rtc and compani on writes operate in a similar manner to memory writes. the distinction is that a different device id is used and only one byte address is needed instead of two. figure 16 illustrates a single byte write to this device. rtc/companion read operation as wit h writes, a read operation begins with the slave address. to perform a register read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. after receiving the complete slave address, the fm31 xx w ill begin shifting data out from the current register address on the next clock. auto - increment operates for the special function registers as with the memory address. a current address read for the registers look exactly like the memory except that the de vice id is different. the fm31 xx contains two separate address registers, one for the memory address and the other for the register address. this allows the contents of one address register to be modified without affecting the current address of the othe r register. for example, this would allow an interrupted read to the memory while still providing fast access to an rtc register. a subsequent memory read will then continue from the memory address where it previously left off, without requiring the load o f a new memory address. however, a write sequence always requires an address to be supplied. figure 1 6 . current address memory read figure 1 7 . sequential memory read s a slave address 1 data byte 1 p by master by fm31xxx start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by fm31xxx start address stop acknowledge no acknowledge data data byte a acknowledge
fm3104/16/64/256 rev. 2.1 sept. 2011 page 20 of 26 figure 1 8 . selective (random) memory read figure 1 9 . byte register write 2 - although not required, it is recommended that a5 - a7 in the register address byte are zeros in order to preserve compatibility with future devices. addressing fram array in the fm31xx family the fm31xx family includes 256kb, 64kb, 16kb , and 4kb memory densities. the following 2 - byte address field is shown for each density. table 4. two - byte memory address part # 1 st address byte 2 nd address byte fm31256 x a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm3164 x x x a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm3116 x x x x x a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm3104 x x x x x x x a8 a7 a6 a5 a4 a3 a2 a1 a0 note: the fm3116 and fm3104 are no longer available. s a slave address 0 address a data byte a p by master start address & data stop acknowledge 0 0 0 by fm31xx s a slave address 1 data byte 1 p by master by fm31xxx start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a
fm3104/16/64/256 rev. 2.1 sept. 2011 page 21 of 26 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any signal pin with respect to v ss - 1.0v to +7.0v * and v in v dd +1.0v ** v bak backup supply voltage - 1.0v to +4.5v t stg storage temperature - 55 ? c to + 125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (jedec std jesd22 - a114 - b) - charged device model (jedec std jesd22 - c101 - a) - machine model (jedec std jesd22 - a115 - a) 2 kv 1 .25 k v 10 0v package moisture sensitivity level msl - 2 * pfi input voltage must not exceed 4.5v. ** the v in < v dd +1.0v restriction does not apply to the scl and sda inputs which do not employ a diode to v dd . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v unless otherwise specified) s ymbol parameter min typ max units notes v dd main power supply voltage 2.7 5.5 v 7 i dd v dd supply current @ scl = 100 khz @ scl = 400 khz @ scl = 1 mhz 500 900 1500 ? a ? a ? a 1 i sb standby current for v dd < 5.5v for v dd < 3.6v 150 120 ? a ? a 2 v bak rtc backup supply voltage @ t a = +25 o c to +85oc @ t a = - 40oc to + 2 5 o c 1. 55 1. 9 3.75 3.75 v v v 9 i bak rtc backup supply current @ t a = +25 o c , v bak = 3.0v @ t a = +85 o c , v bak = 3.0v @ t a = +25oc, v bak = 2.0v @ t a = +85oc, v bak = 2.0v 1 . 4 2. 1 1.15 1.75 ? a ? a ? a ? a 4 i baktc trickle charge current 5 25 ? a 10 v tp0 v dd trip point voltage, vtp(1:0) = 00b 2.55 2.6 2.70 v 5 v tp1 v dd trip point voltage, vtp(1:0) = 01b 2.85 2.9 3.00 v 5 v tp2 v dd trip point voltage, vtp(1:0) = 10b 3.80 3.9 4.00 v 5 v tp3 v dd trip point voltage, vtp(1:0) = 11b 4.25 4.4 4.50 v 5 v rst v dd for valid /rst @ i ol = 80 ? a at v ol v bak > v bak min v bak < v bak min 0 1.6 v v 6 i li input leakage current ? 1 ? a 3 i lo output leakage current ? 1 ? a 3 v il input low voltage all inputs except those listed below cnt1 - 2 battery backed (v dd < 2.5v) cnt1 - 2 (v dd > 2.5v) - 0.3 - 0.3 - 0.3 0.3 v dd 0.5 0.8 v v v 8 v ih input high voltage all inputs except those listed below pfi (comparator input) cnt1 , cnt 2 battery backed (v dd < 2.5v) cnt1 , cnt 2 v dd > 2.5v 0.7 v dd - v bak C 0.5 0.7 v dd v dd + 0.3 3.75 v bak + 0.3 v dd + 0.3 v v v v
fm3104/16/64/256 rev. 2.1 sept. 2011 page 22 of 26 dc operating conditions, continued ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v unless otherwise specified) symbol parameter min typ max units ? notes v ol output low voltage (i ol = 3 ma) - 0.4 v v oh output high voltage (i oh = - 2 ma) 2.4 - v r rst pull - up resistance for /rst inactive 50 400 k ? r in input resistance (pulldown) a1 - a0 for v in = v il max a1 - a0 for v in = v ih min 20 1 k ? m ? v pfi power fail input reference voltage 1.175 1.20 1.225 v v hys power fail input (pfi) hysteresis (rising) - 100 mv notes 1. scl toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v . 2. all inputs at v ss or v dd, static . stop command issued. 3. v in or v out = v ss to v dd . does not appl y to a0, a1, pfi, or /rst pins. 4. v dd < 2.4v, oscillator running, cnt1 - 2 at v bak . 5. /rst is asserted low when v dd < v tp . 6. the minimum v dd to guarantee the level of /rst remains a valid v ol level. 7. full complete operation. supervisory circuits, rtc, etc operate to lower voltages as specified. 8. includes /rst input detection of external reset cond ition to trigger driving of /rst signal by fm31 xx . 9. the vbak trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 10. v bak will source current when trickle charge is enabled (vbc bit=1), v dd > v bak , and v bak < v bak max. ac parameters ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v, c l = 100 pf unless otherwise specified) symbol parameter min max min max min max units notes f scl scl clock frequency 0 100 0 400 0 1000 khz t low clock low period 4.7 1.3 0.6 ? s t high clock high period 4.0 0.6 0.4 ? s t aa scl low to sda data out valid 3 0.9 0.55 ? s t buf bus free before new transmission 4.7 1.3 0.5 ? s t hd:sta start condition hold time 4.0 0.6 0.25 ? s t su:sta start condition setup for repeated start 4.7 0.6 0.25 ? s t hd:dat data in hold time 0 0 0 ns t su:dat data in setup time 250 100 100 ns t r input rise time 1000 300 300 ns 1 t f input fall time 300 300 100 ns 1 t su:sto stop condition setup time 4.0 0.6 0.25 ? s t dh data output hold (from scl @ vil) 0 0 0 ns t sp noise suppression time constant on scl, sda 50 50 50 ns all scl specifications as well as start and stop conditions apply to both read and write operations. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 3.0v) symbol parameter typ max units notes c io input/ o utput c apacitance - 8 pf 1 c xtal x1, x2 crystal pin c apacitance 12 - pf 1, 2 notes 1 this parameter is characterized but not tested. 2 the crystal attached to the x1/x2 pins must be rated as 6pf.
fm3104/16/64/256 rev. 2.1 sept. 2011 page 23 of 26 supervisor timing ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v) symbol parameter min max units notes t rpu /rst a ctive (low) after v dd >v tp 100 200 ms t rnr v dd < v tp noise immunity 10 25 ? s 1 t vr v dd rise time 50 - ? s/v 1,2 t vf v dd fall time 100 - ? s/v 1,2 t wdp pulse width of /rst for watchdog reset 100 200 ms t wdog timeout of watchdog t dog 2*t dog ms 3 f cnt frequency of event counters 0 10 mhz notes 1 this parameter is characterized but not tested. 2 sl ope measured at any point on v dd waveform . 3 t dog is the programmed time in register 0ah, v dd > v tp and t rpu satisfied. /rst timing data retention ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 5.5v) symbol parameter min units notes t dr data retention @ +75c @ +80c @ +85c 38 19 10 years years years vdd vtp vrst rst t rpu t rnr
fm3104/16/64/256 rev. 2.1 sept. 2011 page 24 of 26 ac test conditions equivalent ac load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing wri te bus timing t su : sta start t r ` t f stop start t buf t high 1 / f scl t low t sp t sp acknowledge t hd : dat t su : d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda 5.5v output 1700 ? 100 pf
fm3104/16/64/256 rev. 2.1 sept. 2011 page 25 of 26 mechanical drawing 14 - pin soic (jedec standard ms - 012 variation ab) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxx xx x= part number, p= package type ( g =green /rohs ) r=rev, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm31256, green soic package, year 20 11 , work week 0 6 fm31256 - g d 9 000 7 g1 ric 110 6 xxxx xxx - p r ll llll l ric yyww pin 1 3 . 90 0 . 13 6 . 00 0 . 20 8 . 64 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 ? 0 . 40 1 . 27 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70 . . . . . .
fm3104/16/64/256 rev. 2.1 sept. 2011 page 26 of 26 revision history revision date summary 2 .0 1/ 31 /201 1 pre - production status. rev d. changed i bak and v bak specs. added curves to backup power section (p.7). 2.1 9/ 12 /2011 fm3116 and fm3104 are end of life (eol) . there are no direct replacements for these parts. the fm31256 and fm3164 are unaffected by th is change.

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